------------------------------------
-- TINA VHDL Macro
-- entity_name:e_half_add_entity
-- arch_name:a_half_add_arch
-- ports:A,B;S,C
------------------------------------

LIBRARY ieee, tina_lib, tina_misc;
use ieee.std_logic_1164.all;
use std.textio.all;
USE tina_lib.primitives.all;
USE tina_misc.misc_primitives.all;

------------------------------------
-- entity section                   
------------------------------------
ENTITY e_half_add_entity IS PORT(
  A : IN std_logic; 
  S : OUT std_logic; 
  C : OUT std_logic; 
  B : IN std_logic );
END e_half_add_entity;

------------------------------------
-- architecture section
------------------------------------
ARCHITECTURE a_half_add_arch of e_half_add_entity IS

 signal zero : std_logic := '0';
 signal one  : std_logic := '1';

 signal N5 : std_logic;
 signal N6 : std_logic;

BEGIN



INIT_COMPS: process( N5, N6, C, A, B )
begin
 S <=  ( N5 AND N6 ) AFTER 23 ns;
 N6 <= NOT ( C ) AFTER 18.5 ns;
 C <=  ( A AND B ) AFTER 23 ns;
 N5 <=  ( A OR B ) AFTER 18.5 ns;
end process INIT_COMPS;


END a_half_add_arch;

